As my Fall 2021 semester comes to a close, I made the final commits to perhaps one of the most interesting projects I’ve had the pleasure of stressing about thus far in school: building a file system. Err–okay, I won’t sit here and pretend that my classmates and I built out fully fledged filesystems ready to be thrown into Ubuntu for production. However, that wasn’t quite the point of this assignment....
As a conclusion to my computer organization course, our final project was to implement a five stage pipeline constructed in Verilog over an FPGA partially implementing the MIPS instruction set. Abstract The following details the development of a five stage pipeline constructed on Xilinx’s Vivado in Verilog over an FPGA partially implementing the MIPS instruction set. In its current configuration, it supports only basic R-Format instructions like add, sub, and, or, etc....
Note: This is more of just a retrospective post. I worked on this whole ordeal about a year ago and am only now finding the time to really document it. I just figured I’d throw up a few pictures of it and talk a little bit about it. Last winter break I became obsessed with individually addressable LEDs. More specifically, I was interested in controlling them. Soon enough, I found myself lost in the world of ESP based controllers and almost sank entirely into the home-assistant/home-automation world trying to find a good controller that...