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As my fourth semester was just wrapping up, I was getting ready to take a few much needed weeks off before work and unwind just a little bit. Two days after my last final, however, I found out about Chia. Needless to say, I guess I never got to stop! Fortunately for me and many other homelab and mining enthusiasts, farming Chia is a lot of fun. And by fun, I mean spending ludacris amounts of money on enterprise hardware that we would otherwise never have an excuse to buy....

As a conclusion to my computer organization course, our final project was to implement a five stage pipeline constructed in Verilog over an FPGA partially implementing the MIPS instruction set. Abstract The following details the development of a five stage pipeline constructed on Xilinx’s Vivado in Verilog over an FPGA partially implementing the MIPS instruction set. In its current configuration, it supports only basic R-Format instructions like add, sub, and, or, etc....

Each year, Penn State New Kensington holds their Research and Student Engagement Expo where Penn State students like myself get to present their research findings to faculty and other students. Despite being held virtually as a consequence of the Pandemic, all of us seemed to persevere and come through with some really interesting projects and topics. You can find the main page for all of the projects here. As a Sophomore in the Penn State New Kensington Honors Program, this was my year to participate!...

Note: This is more of just a retrospective post. I worked on this whole ordeal about a year ago and am only now finding the time to really document it. I just figured I’d throw up a few pictures of it and talk a little bit about it. Last winter break I became obsessed with individually addressable LEDs. More specifically, I was interested in controlling them. Soon enough, I found myself lost in the world of ESP based controllers and almost sank entirely into the home-assistant/home-automation world trying to find a good controller that...